No. 1 (2005)
Published:
2005-03-30
ARTICLES FROM THIS ISSUE
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Challenges in scaling of CMOS devices towards 65 nm node
Abstract
The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scaling in traditional way due to fundamental limitations like resolution, quantum effects or random fluctuations. In turn, this has an important impact on electrical device specifications especially leakage current and the circuit power dissipation.
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Gate dielectrics: process integration issues and electrical properties
Abstract
In this work we report on the process integration of crystalline praseodymium oxide (Pr2O3) high-k gate dielectric. Key process steps that are compatible with the high-k material have been developed and were applied for realisation of MOS structures. For the first time Pr2O3 has been integrated successfully in a conventional MOS process with n poly-silicon gate electrode. The electrical properties of Pr2O3 MOS capacitors are presented and discussed.
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Understanding of wet and alternative particle removal processes in microelectronics: theoretical capabilities and limitations
Abstract
A 2 orders of magnitude range of van der Waals interactions is considered here to take the majority of the variety of shapes and materials of actual particles into account. Comparing these interactions with the repulsive forces generated by electrostatic charges, drag, surface tension, shock waves, high accelerations and aerosol particles, the intrinsic capabilities and limitations of the different cleaning processes can be predicted. Three kinds of particle-removal processes have been identified -- universal processes capable of removing all particle sizes and types, even from patterned wafers, processes that present the same theoretical ability but are actually limited by the accessibility of the particles, and finally cleanings that are not able to remove all particle sizes.
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Integrated gas chromatograph
Abstract
A portable gas chromatograph with integrated micromachined flushed injector and thermal mass detector (TCD) has been developed. The silicon/glass injector operates in a fixed volume (2 x 7} uL or electronically operated mode. An integrated, pneumatically operated, fast cross-valve is applied in the injector. The TCD detector consists of two Pt microheaters and thermoresistors packaged in a silicon/glass micromachined chip. The temperature of two capillary molecular sieve separation columns is controlled by a thick-film heater fabricated on polyimide foil. The chromatograph is equipped with two 16-bits microprocessors communicating with the external portable PC. The instrument may operate in the on-line continuous analysis mode.
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Low frequency noise in advanced Si bulk and SOI MOSFETs
Abstract
A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental data obtained on advanced CMOS SOI and Si bulk generations. Furthermore, the impact on the electrical noise of the shrinking of CMOS devices in the deep submicron range is also shown. The main physical characteristics of random telegraph signals (RTS) observed in small area MOS transistors are reviewed. Experimental results obtained on 0.35-0.12 um CMOS technologies are used to predict the trends for the noise in future CMOS technologies, e.g., 0.1 um and beyond. For SOI MOSFETS, the main types of layout will be considered, that is floating body, DTMOS, and body-contact. Particular attention will be paid to the floating body effect that induces a kink-related excess noise, which superimposes a Lorentzian spectrum on the flicker noise.
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Variability of the local φMS values over the gate area of MOS devices
Abstract
The local value distributions of the effective contact potential difference (ECPD or the φMS factor) over the gate area of Al-SiO2-Si structures were investigated for the first time. A~modification of the photoelectric φMS measurement method was developed, which allows determination of local values of this parameter in different parts of metal-oxide-semiconductor (MOS) structures. It was found that the φMS distribution was such, that its values were highest far away from the gate edge regions (e.g., in the middle of a square gate), lower in the vicinity of gate edges and still lower in the vicinity of gate corners. These results were confirmed by several independent photoelectric and electrical measurement methods. A model is proposed of this distribution in which the experimentally determined φMS distributions, found previously, are attributed to mechanical stress distributions in MOS structures. Model equations are derived and used to calculate φMS distributions for various structures. Results of these calculations remain in agreement with experimentally obtained distributions. Comparison of various characteristics calculated using the model with the results of photoelectric and electrical measurements of a wide range of Al-SiO2-Si structures support the validity of the model.
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Diagnostics of micro- and nanostructure using the scanning probe microscopy
Abstract
In this paper we summarize the results of our research concerning the diagnostics of micro- and nanostructure with scanning probe microscopy (SPM). We describe the experiments performed with one of the scanning probe microscopy techniques enabling also insulating surfaces to be investigated, i.e., atomic force microscopy (AFM). We present the results of topography measurements using both contact and non-contact AFM modes, investigations of the friction forces that appear between the microtip and the surface, and experiments connected with the thermal behaviour of integrated circuits, carried out with the local resolution of 20 nm.
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An accurate prediction of high-frequency circuit behaviour
Abstract
An accurate way to predict the behaviour of an RF analogue circuit is presented. A lot of effort is required to eliminate the inaccuracies that may generate the deviation between simulation and measurement. Efficient use of computer-aided design and incorporation of as many physical effects as possible overcomes this problem. Improvement of transistor modelling is essential, but there are many other unsolved problems affecting the accuracy of RF analogue circuit modelling. In this paper, the way of selection of accurate transistor model and the extraction of parasitic elements from the physical layout, as well as implementation to the circuit simulation will be presented using two CMOS circuit examples: an amplifier and a voltage controlled oscillator (VCO). New simulation technique, electro-magnetic (EM)-co-simulation is introduced.
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Trends in assembling of advanced IC packages
Abstract
In the paper, an overview of the current trends in the development of advanced IC packages will be presented. It will be shown how switching from peripheral packages (DIP, QFP) to array packages (BGA, CSP) and multichip packages (SiP, MCM) affects the assembly processes of IC and performance of electronic systems. The progress in bonding technologies for semiconductor packages will be presented too. The idea of wire bonding, flip chip and TAB assembly will be shown together with the boundaries imposed by materials and technology. The construction of SiP packages will be explained in more detail. The paper addresses also the latest solutions in MCM packages.
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Ultra-shallow nitrogen plasma implantation for ultra-thin silicon oxynitride (SiOxNy) layer formation
Abstract
The radiation damage caused by low energy r.f. plasmas has not been, to our knowledge, studied so far in the case of symmetric planar plasma reactors that are usually used for PECVD processes. The reason is that, unlike non-symmetrical RIE reactors, such geometry prevents, basically, high-energy ion bombardment of the substrate. In this work, we present the results of experiments in which we have studied the influence of plasma processing on the state of silicon surface. Very low temperature plasma oxidation has been used as a test of silicon surface condition. The obtained layers were then carefully measured by spectroscopic ellipsometry, allowing not only the thickness to be determined accurately, but also the layer composition to be evaluated. Different plasma types, namely N2, NH3 and Ar, were used in the first stage of the experiment, allowing oxidation behaviour caused by the exposure to those plasma types to be compared in terms of relative differences. It has been clearly proved that even though the PECVD system is believed to be relatively safe in terms of radiation damage, in the case of very thin layer processing (e.g., ultra-thin oxynitride layers) the effects of radiation damage may considerably affect the kinetics of the process and the properties of the formed layers.
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Properties of Al contacts to Si surface exposed in the course of plasma etching of previously grown nanocrystalline c-BN film
Abstract
Properties of Al electric contacts to Si(p) surface exposed to fluorine-based plasma etching of nanocrystalline cubic boron nitride (c-BN) film grown previously were studied and compared to the properties of Al contacts fabricated on pristine or dry etched surface of Si(p) wafers. In addition, a part of the investigated samples was annealed in nitrogen atmosphere at the temperature of 673 K. Analysis of contract properties is based on current-voltage (I-V) measurements of the produced Al-Si structures. The presented investigations were performed in order to evaluate the efficiency of the applied plasma etching method of nanocrystalline c-BN from the viewpoint of its influence on the properties of metal contacts formed subsequently and thus on the performance of electronic devices involving the use of boron nitride.
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Application of scanning shear-force microscope for fabrication of nanostructures
Abstract
In view of the rapid growth of interest in AFM technique in surface property investigation and local surface modification we describe here an AFM microscope with optical tip oscillation detection. The modular shear-force/tunneling microscope for surface topography measurement and nanoanodisation is described. The measurement instrument presented here is based on the fiber Fabry-Perot interferometer for the measurement of the conductive microtip oscillation that is used as nano e-beam for local surface anodisation. An advantage of this system is that quatitative measurements of tip vibration amplitude are easily performed.
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TSSOI as an efficient tool for diagnostics of SOI technology in Institute of Electron Technology
Abstract
This paper reports a test structure for characterization of a new technology combining a standard CMOS process with pixel detector manufacturing technique. These processes are combined on a single thick-film SOI wafer. Preliminary results of the measurements performed on both MOS SOI transistors and dedicated SOI test structures are described in detail.
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Silicon TCD for the methane and carbon monoxide detection
Abstract
Analytical model, design principles, technology and test results concerning a thermal conductivity detector (TCD) are presented. Prototype TCD units fabricated using the standard silicon IC VLSI and MEMS techniques are reported. The detectors are integrated with gas separation columns and micro-valve dosing systems. Initial tests were carried out in a gas mixture containing methane, carbon monoxide, oxygen, hydrogen and nitrogen.
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Gas micro-flow-metering with the in-channel Pt resistors
Abstract
Standard thermo-conductive gas flow meters have the side-channel integrated with the temperature detector and heater coils, both winded around the tube. This design suffers from a high thermal capacity, reduced sensitivity in the lower limit flow range, high thermal inertia, long response time and necessity to amplify electronically the output signal. The newly designed TCD detector can be applied as a precise gas flow meter. To identify the composition of the unknown gas, the TCD unit requires a connection to the separation column, application of the reference channel and highly stable flow rate regulator. To measure flow rates, the same TCD unit requires only one flow channel application, with active resistors inside it, and a definition of the gas type. In this work principles of the TCD design, technology and flow rate sensitivity tests are presented.
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DC and low-frequency noise analysis for buried SiGe channel metamorphic PMOSFETs with high Ge content
Abstract
Measurements of current drive in p-Si1-xGex MOSFETs, with x = 0.7, 0.8 reveal an enhancement ratio of over 2 times as compared to a Si device at an effective channel length of 0.55 um. They also show a lower knee voltage in the output I-V characteristics while retaining similar values of drain induced barrier lowering, subthreshold swing, and off current for devices with a Sb punch-through stopper. For the first time, we have quantitatively explained the low-frequency noise reduction in metamorphic, high Ge content, SiGe PMOSFETs compared to Si PMOSFETs.
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Photoelectric measurements of the local values of the effective contact potential difference in the MOS structure
Abstract
We have shown that using focused UV laser beam in photoelectric methods it is possible to measure local φMS values over the gate area of a single MOS structure. The φMS distribution is such that its values are highest far away from the gate edges regions, lower in the vicinity of gate edges and still lower in the vicinity of gate corners. Examples of measurement results and description of the measurement system are presented. The dependence of the φMS value on the exposure time and the power density of UV light is discussed.
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Effects of stress annealing on the electrical and the optical properties of MOS devices
Abstract
In this paper we show the results of a study of the effects of high-temperature stress annealing in nitrogen on the refraction index of SiO2 layers and electrical properties in metal-oxide-semiconductor (MOS) devices. We have experimentally characterized the dependence of the reduced effective contact potential difference (ECPD), the effective oxide charge density (Neff), and the mid-gap interface trap density (Dit) on the annealing conditions. Subsequently, we have correlated such properties with the dependence of the refraction index and oxide stress on the annealing conditions and silicon dioxide thickness. Also, the dependence of mechanical stress in the Si-SiO2 system on the oxidation and annealing conditions has been experimentally determined. We consider the contributions of the thermal-relaxation and nitrogen incorporation processes in determining changes in the SiO2 layer refractive index and the electrical properties with annealing time. This description is consistent with other annealing studies carried out in argon, where only the thermal relaxation process is present.
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Comparison of the barrier height measurements by the Powell method with the φMS measurement results
Abstract
In this work, we have compared the barrier height measurements carried out using the Powell method with the photoelectric effective contact potential difference (φMS) measurement results. The photoelectric measurements were performed on the samples that were previously applied in the investigation of the influence of stress on the duration of annealing in nitrogen. This paper shows that the results of barrier height measurement using the Powell method differ significantly from the φ(MS) measurement results.
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Semi-automatic test system for characterization of ASIC/MPWS
Abstract
A measurement system for integrated circuit testing has been developed. It consists of a semi-automatic probe station and a set of measurement equipment controlled by commercially available measurement software. The probe station is controlled by dedicated software. Both the measurement and station-control software communicate using the DDE protocol. The measurement system is flexible. It is particularly suitable for semi-automatic testing of multi-project wafers. Output data generated by the system is used for the characterization of the CMOS technologies.
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A versatile tool for extraction of MOSFETs parameters
Abstract
Extraction of MOSFET parameters is a very important task for the purposes of MOS integrated circuits characterization and design. A versatile tool for the MOSFET parameter extraction has been developed in the Institute of Electron Technology (IET). It is used to monitor the technologies applied for fabrication of several groups of devices, e.g., CMOS ASICs, SOI pixel detectors. At present two SPICE MOSFET models (LEVEL = 1, 2) have been implemented in the extraction tool. The LEVEL = 3 model is currently being implemented. The tool combines different methods of parameter extraction based on local as well as global fitting of models to experimental data.
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Standardization of the compact model coding: non-fully depleted SOI MOSFET example
Abstract
The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.
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A new method of frequency offset correction using coherent averaging
Abstract
This paper describes a new method of frequency offset correction to improve clock stability in communication systems where the temporary drift or jitter of phase angle is not accepted. This method bases on coherent spectral averaging with a special phase scanning algorithm. Achieved results show that proposed method is effective for strongly degraded signals. Method is useful for precise phase angle reconstruction in these systems where clock stability of the transceiver and receiver is insufficient.
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Comparison of traffic performance of QPSK and 16-QAM modulation techniques for OFDM system
Abstract
Orthogonal frequency division multiplexing (OFDM) provides better spectral efficiency than frequency division multiplexing (FDM), while maintaining orthogonal relation between carriers; hence traffic is better carried by OFDM than FDM within the same spectrum. This paper reveals a comparison of spectral efficiency, performance of communication system in context of bit error rate (BER) for the same information rate and peak to average power ratio (PAPR) of quadrature amplitude shift keying (QPSK) and 16-quadrature amplitude modulation (16-QAM) technique.
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A newly developed random walk model for PCS network
Abstract
Different types of random walk models are prevalent in mobile cellular network for analysis of roaming and handover, being considered as important parameters of traffic measurement and location updating of such network. This paper proposes a new random walk model of hexagonal cell cluster, exclusively developed by the authors and a comparison is made with two existing models. The proposed model shows better performance in context of number of probability states compared to existing models.
