Challenges in scaling of CMOS devices towards 65 nm node

Authors

  • Małgorzata Jurczak
  • Ivan Pollentier
  • Simone Severi
  • Kirklen Henson
  • Anne Lauwers
  • Richard Lindsay
  • Marc Scaekers
  • Aude Rotschild
  • Sofie Mertens
  • Emmanuel Augendre
  • Rita Rooyackers
  • Anabela Veloso
  • An de Keersgieter

DOI:

https://doi.org/10.26636/jtit.2005.1.299

Keywords:

CMOS devices, gate dielectrics, shallow junctions, silicide, gate stack, lithography, gate patterning, silicon recess, device integration

Abstract

The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scaling in traditional way due to fundamental limitations like resolution, quantum effects or random fluctuations. In turn, this has an important impact on electrical device specifications especially leakage current and the circuit power dissipation.

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Published

2005-03-30

Issue

No. 1 (2005)

Section

ARTICLES FROM THIS ISSUE

License

Copyright (c) 2005 Journal of Telecommunications and Information Technology

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
M. Jurczak, “Challenges in scaling of CMOS devices towards 65 nm node”, JTIT, vol. 19, no. 1, pp. 3–6, Mar. 2005, doi: 10.26636/jtit.2005.1.299.