No. 2 (2007)

Published: 2007-06-30

ARTICLES FROM THIS ISSUE

  • Preface

    Abstract

    Preface

    Andrzej Jakubowski, Lidia Łukasiak
  • SOI nanodevices and materials for CMOS ULSI

    Abstract

    A review of recently explored new effects in SOI nanodevices and materials is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAMare also outlined.

    Francis Balestra
    3-13
  • Special size effects in advanced single-gate and multiple-gate SOI transistors

    Abstract

    State-of-the-art SOI transistors require a very small body. This paper examines the effects of body thinning and thin-gate oxide in SOI MOSFETs on their electrical characteristics. In particular, the influence of film thickness on the interface coupling and carrier mobility is discussed. Due to coupling, the separation between the front and back channels is difficult in ultra-thin SOI MOSFETs. The implementation of the front-gate split C-V method and its limitations for determining the front- and back-channel mobility are described. The mobility in the front channel is smaller than that in the back channel due to additional Coulomb scattering. We also discuss the 3D coupling effects that occur in FinFETs with triple-gate and omega-gate configurations. In low-doped or tall fins the corner effect is suppressed. Narrow devices are virtually immune to substrate effects due to a strong lateral coupling between the two lateral sides of the gate. Short-channel effects are drastically reduced when the lateral coupling screens the drain influence.

    Akiko Ohata, Romain Ritzenthaler, Olivier Faynot, Sorin Cristoloveanu
    14-24
  • Challenges for 10 nm MOSFET process integration

    Abstract

    An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.

    Mikael Östling, Bengt Gunnar Malm, Martin von Haartman, Julius H ̊allstedt, Zhen Zhang, Per-Erik Hellström, Shili Zhang
    25-32
  • Review and perspective of high-k dielectrics on silicon

    Abstract

    The paper reviews recent work in the area of high-k dielectrics for application as the gate oxide in advanced MOSFETs. Following a review of relevant dielectric physics, we discuss challenges and issues relating to characterization of the dielectrics, which are compounded by electron trapping phenomena in the microsecond regime. Nearly all practical methods of preparation result in a thin interfacial layer generally of the form SiOx or a mixed oxide between Si and the high-k so that the extraction of the dielectric constant is complicated and values must be qualified by error analysis. The discussion is initially focussed on HfO2 but recognizing the propensity for crystallization of that material at modest temperatures, we discuss and review also, hafnia silicates and aluminates which have the potential for integration into a full CMOS process. The paper is concluded with a perspective on material contenders for the “end of road map” at the 22 nm node.

    Stephe Hall, Octavian Buiu, Ivona Z. Mitrovic, Yi Lu, William M. Davey
    33-43
  • Semiconductor cleaning technology for next generation material systems

    Abstract

    This paper gives a brief overview of the challenges wafer cleaning technology is facing in the light of advanced silicon technology moving in the direction of non-planar device structures and the need for modified cleans for semiconductors other than silicon. In the former case, the key issue is related to cleaning and conditioning of vertical surfaces in next generation CMOS gate structure as well as deep 3D geometries in MEMS devices. In the latter, an accelerated pace at which semiconductors other than silicon are being introduced into the mainstream manufacturing calls for the development of material specific wafer cleaning technologies. Examples of the problems related to each challenge are considered.

    Jerzy Ruzyllo
    44-48
  • Development of 3C-SiC MOSFETs

    Abstract

    The paper reviews the development of the 3C-SiC MOSFETs in a unique development project combining the material and device expertise of HAST (Hoya Advanced Semiconductor Technologies) and Acreo, respectively. The motivation for the development of the 3C-SiC MOSFETs and the summary of the results from the lateral and vertical devices with varying size from single cell to 3×3 mm2 large devices are reviewed. The vertical devices had hexagonal and square unit cell designs with 2 μm and 4 μm channel length. The p-body was aluminum implanted and the source was nitrogen or phosphorus implanted. Low temperature Ti/W contacts were evaluated.

    Mietek Bakowski, Adolf Schöner, Per Ericsson, Helena Strömberg, Hiroyuki Nagasawa, Masayuki Abe
    49-56
  • Properties and benefits of fluorine in silicon and silicon-germanium devices

    Abstract

    This paper reviews the behaviour of fluorine in silicon and silicon-germanium devices. Fluorine is shown to have many beneficial effects in polysilicon emitter bipolar transistors, including higher values of gain, lower emitter resistance, lower 1/f noise and more ideal base characteristics. These results are explained by passivation of trapping states at the polysilicon/silicon interface and accelerated break-up of the interfacial oxide layer. Fluorine is also shown to be extremely effective at suppressing the diffusion of boron, completely suppressing boron transient enhanced diffusion and significantly reducing boron thermal diffusion. The boron thermal diffusion suppression correlates with the appearance of a fluorine peak on the SIMS profile at approximately half the projected range of the fluorine implant, which is attributed to vacancy- fluorine clusters. When applied to bipolar technology, fluorine implantation leads to a record fT of 110 GHz in a silicon bipolar transistor.

    Peter Ashbur, Huda A. W. El Mubarek
    57-63
  • Low frequency noise in Si and Si/SiGe/Si PMOSFETs

    Abstract

    Measurements of 1/f noise in Si and Si0.64Ge0.36 PMOSFETs have been compared with theoretical models of carrier tunnelling into the oxide. Reduced noise is observed in the heterostructure device as compared to the Si control. We suggest that this is primarily associated with an energy dependent density of oxide trap states and a displacement of the Fermi level at the SiO2 interface in the heterostructure relative to Si. The present study also emphasizes the important role of transconductance enhancement in the dynamic threshold mode in lowering the input referred voltage noise.

    Stephen M. Thomas, Marti J. Prest, Dominic J. F. Fulgoni, Adam R. Bacon, Tim J. Grasby, David R. Leadley, Evan H. C. Parker, Terence E. Whall
    64-68
  • On-wafer wideband characterization: a powerful tool for improving the IC technologies

    Abstract

    In the present paper, the interest of wideband characterization for the development of integrated technologies is highlighted through several advanced devices, such as 120 nm partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, 120 nm dynamic threshold (DT) voltage – SOI MOSFETs, 50 nm FinFETs as well as long-channel planar double gate (DG) MOSFETs.

    Dimitri Lederer, Jean-Pierre Raskin
    69-77
  • Evaluation of MOSFETs with crystalline high-k gate-dielectrics: device simulation and experimental data

    Abstract

    The evaluation of the world’s first MOSFETs with epitaxially-grown rare-earth high-k gate dielectrics is the main issue of this work. Electrical device characterization has been performed on MOSFETs with high-k gate oxides as well as their reference counterparts with silicon dioxide gate dielectric. In addition, by means of technology simulation with TSUPREM4, models of these devices are established. Current-voltage characteristics and parameter extraction on the simulated structures is conducted with the device simulator MEDICI. Measured and simulated device characteristics are presented and the impact of interface state and fixed charge densities is discussed. Device parameters of high-k devices fabricated with standard poly-silicon gate and replacement metal gate process are compared.

    Florian Zaunert, Ralf Endres, Yordan Stefanov, Udo Schwalke
    78-85
  • Energy concepts involved in MOS characterization

    Abstract

    Starting from a quantum statistical reasoning, it is demonstrated that entropy properties of silicon/silicon dioxide interface electron traps may have a strong influence on measured distributions of interface states, depending on measurement method used. For methods, where the Fermi-level is used as a probe to define an energy position, the scale is based on free energy. On the other hand, methods based on thermal activation of electrons give the distribution on an enthalpy scale. It is shown that measured interface state distributions are influenced by the distribution of entropy, and that common features of measured energy distributions may be influenced by entropy variations. These results are used to interpret experimental data on the energy distribution of electron capture cross sections with an exponential increase followed by a more or less constant value as the energy distance of the traps from the conduction band edge increases. Such a relation is shown to be consistent with a situation where the emission and capture processes of electrons obey the Meyer-Neldel rule.

    Olof Engström, Tomasz Gutt, Henryk M. Przewłocki
    86-91
  • Modeling of negative bias temperature instability

    Abstract

    Negative bias temperature instability is regarded as one of the most important reliability concerns of highly scaled PMOS transistors. As a consequence of the continuous downscaling of semiconductor devices this issue has become even more important over the last couple of years due to the high electric fields in the oxide and the routine incorporation of nitrogen. During negative bias temperature stress a shift in important parameters of PMOS transistors, such as the threshold voltage, subthreshold slope, and mobility is observed. Modeling efforts date back to the reaction-diffusion model proposed by Jeppson and Svensson thirty years ago which has been continuously refined since then. Although the reaction-diffusion model is able to explain many experimentally observed characteristics, some microscopic details are still not well understood. Recently, various alternative explanations have been put forward, some of them extending, some of them contradicting the standard reaction-diffusion model. We review these explanations with a special focus on modeling issues.

    Tibor Grasser, Siegfried Selberherr
    92-102
  • Modeling of voice data integrated traffic in 3G mobile cellular network

    Abstract

    The most important feature of 3G mobile cellular network is introduction of voice data integrated service under multilayered cell environment to support overflow traffic of lower layered cells by upper ones. This paper deals with traffic model of three layered cells, i.e., micro cell, macro cell and satellite cell. Here a new call admission control is introduced for three layered cell of 3G mobile cellular network. State transition chain is designed for theoretical analysis of above mentioned traffic. Blocking probability of data call, new voice call and handover failure of voice call, probability of utilization of micro cell channel, macro cell channel and satellite cell channel are analyzed against different traffic parameters and yield logical results.

    Imdadul Islam, Jugal Krishna Das, Siddique Hossain
    103-108
  • Simple method for characterization of photonic crystal fibers

    Abstract

    We report on our experimental characterization of index-guiding photonic crystal fibers (PCF) from their far field intensity distribution. The algorithm presented below makes it possible to determine the geometrical parameters of the PCF (core diameter, air hole spacing and air hole diameter) from its far field pattern. We obtained good agreement with the manufacturer’s data for all fibers tested.

    Mieczysław Szustakowski, Norbert Pałka, Waldemar Grabiec
    109-113
  • Availability analysis and comparison of different WDM systems

    Abstract

    We begin reasons why high system availability is important. Furthermore, the basic terms are introduced pertaining to the availability with particular review of the parallel structure. Then the availability of different wavelength division multiplexing (WDM) systems is analysed: point to point, chain and ring with 1+1 protection of the wavelength channel, plus the influence of availability of nodes and links on the total system availability. The data on failure intensity and mean time to repair of certain components were taken from various literature sources. We assumed in the analysis a WDM system with 16 wavelengths and 2.5 Gbit/s capacity per wavelength channel. Finally, results of calculation and comparisons of availability of different WDM systems and proposals for improvement of their availability are presented.

    Ivan Rados
    114-119