Challenges for 10 nm MOSFET process integration

Authors

  • Mikael Östling
  • Bengt Gunnar Malm
  • Martin von Haartman
  • Julius H ̊allstedt
  • Zhen Zhang
  • Per-Erik Hellström
  • Shili Zhang

DOI:

https://doi.org/10.26636/jtit.2007.2.805

Keywords:

sstrained silicon, silicon germanium, silicon-oninsulator (SOI), high-k dielectrics, hafnium oxide, nano-wire, low-frequency noise, mobility, metal gate

Abstract

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.

Downloads

Download data is not yet available.

Downloads

Published

2007-06-30

Issue

No. 2 (2007)

Section

ARTICLES FROM THIS ISSUE

License

Copyright (c) 2023 Journal of Telecommunications and Information Technology

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
M. Östling, “Challenges for 10 nm MOSFET process integration”, JTIT, vol. 28, no. 2, pp. 25–32, Jun. 2007, doi: 10.26636/jtit.2007.2.805.