No. 3-4 (2000)

Published: 2000-12-30

Preface

  • Preface

    Abstract

    Preface

    Andrzej Jakubowski, Aleksander Werbowy, Lidia Lukasiak

ARTICLES FROM THIS ISSUE

  • Silicon-germanium for ULSI

    Abstract

    The paper describes recent progress for the introduction of silicon-germanium, bipolar and field effect heterostructure transistors into mainstream integrated circuit application. Basic underlying concepts and device architectures which give rise to the desired performance advantages are described together with the latest state-of the-art results for HBT and MOSFET devices. The integration of such devices into viable HBT, BiCMOS and CMOS is reviewed. Other contributions that SiGe can make to enhance the performance of ULSI circuits are mentioned also.

    Steve Hall, Bill Eccleston
    3-9
  • CVD growth of high speed SiGe HBTs using SiH4

    Abstract

    The growth of high frequency HBT structures using silane-based epitaxy has been studied. The integrity of SiGe layers in the base and the control of the collector profile using As- or P-doping grown at 650 oC have been investigated. The results showed that the growth rate of SiGe layers has a strong effect on the evolution of defect density in the structure. Furthermore, B-doped SiGe layers have a~higher thermal stability compared to undoped layers. The analysis of the collector profiles showed a higher incorporation of P in silane-based epitaxy compared to As. Meanwhile, the growth of As- or P-doped layers on the patterned substrates suffered from a high loading effect demanding an accurate calibration.

    Henry H. Radamson, Jan Grahn, Gunnar Landgren
    10-14
  • Optimization of selected parameters of SiGe HBT transistors

    Abstract

    SiGe-base HBTs with Gaussian doping distribution are modeled including the effect of the drift field and variable Ge concentration in the base on the diffusion coefficient. Two different Ge distributions in the base are considered: a triangular one and a box one the patterned substrates suffered from a high loading effect demanding an accurate calibration.

    Agnieszka Zaręba, Andrzej Jakubowski
    15-18
  • Roadmap for SiC power devices

    Abstract

    Silicon carbide (SiC) power devices offer significant benefits of improved efficiency, dynamic performance and reliability of electronic and electric systems. The challenges and prospects of SiC power device development are reviewed considering different device types. A close correlation between an exponential increase of current handling capability during recent five years and improvement in substrate quality is demonstrated. The voltage range of silicon and SiC unipolar and bipolar power devices with respect to the on-state voltage is determined based on device simulation. 4H-SiC unipolar devices are potentially superior to all silicon devices up to 10 kV. 4H-SiC unipolar devices are superior to all SiC bipolar devices up to 8-9 kV. The low end of SiC unipolar devices is determined to be around 200 V provided substrate resistance is reduced by thinning the substrate down to 100 um. The influence of reduced channel mobility on the specific on-state resistance of 4H-SiC DMOSFETs and UMOSFETs is shown. It has been demonstrated that 6H-SiC DMOSFETs could be a better choice compared to 4H-SiC MOSFETs in the voltage range below 600 V utilising better channel mobility obtainable so far on 6H-SiC polytype. An impact of super junction (SJ) concept on silicon and SiC MOSFET specific on-resistance limits is demonstrated

    Mietek Bakowski
    19-30
  • Advanced compact modeling of the deep submicron technologies

    Abstract

    The technology of CMOS large-scale integrated circuits (LSI`s) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 um LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model

    Władysław Grabiński, Matthias Bucher, Jean-Michel Sallese, François Krummenacher
    31-42
  • On the extraction of threshold voltage, effective channel length and series resistance of MOSFETs

    Abstract

    The first part of this article presents the modeling of the long-channel bulk MOSFET as a particular case of the SOI MOSFET. The second part reviews compares and scrutinizes various methods to extract the threshold voltage, the effective channel and the individual values of drain and source resistances. These are important device parameters for modeling and circuit simulation

    Adelmo Ortiz-Conde, Francisco J. García Sánchez, Juin J. Liou
    43-58
  • Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs

    Abstract

    Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal model element. Knowing the qualitative small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process

    Michel Goffioul, Danielle Vanhoenacker, Jean-Pierre Raskin
    59-66
  • An impact of frequency on capacitances of partially-depleted SOI MOSFETs

    Abstract

    A non-quasi-static model of partially-depleted SOI MOSFETs is presented. Phenomena, which are particularly responsible for dependence of device admittances on frequency are briefly described. Several C-V characteristics of the SOI MOSFET calculated for a wide range of frequencies, preliminary results of numerical analysis and of measurements and brief analysis of the results are presented. Methods of model improvement are proposed

    Lidia Łukasiak, Agnieszka Zaręba, Andrzej Jakubowski, Daniel Tomaszewski
    67-72
  • Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs

    Abstract

    The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD) and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lengths and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 um FD SOI n-MOSFETs with a total gate width of 100 um present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for Vds=0.75

    Michael Goffioul, Gilles Dambrine, Danielle Vanhoenacker, Jean-Pierre Raskin
    72-80
  • Characterization of SOI fabrication process using gated-diode measurements and TEM studies

    Abstract

    SOI fabrication process was characterized using electrical and TEM methods. The investigated SOI structures included partially and fully depleted capacitors, gated diodes and transistors fabricated on SIMOX substrates. From C-V and I-V measurements of gated diodes, the following parameters of partially depleted structures were determined: doping concentration in both n- and p-type regions, average carrier generation lifetimes in the region under the gate and generation velocity at top and bottom surfaces of the active layer. Structures with short lifetime were studied using a transmission electron microscope. TEM studies indicate that the quality of the active layer in the investigated structures is good. Moreover, these studies were used to verify the thicknesses determined by means of electrical characterization methods.

    Jerzy Katcki, Jacek Ratajczak, Andrzej Jakubowski, Lidia Łukasiak, Daniel Tomaszewski, Jan Gibki
    81-83
  • Characterization of the indoor radio propagation channel at 2.4 GHz

    Abstract

    The unlicensed industrial, scientific, and medical (ISM) band at 2.4 GHz has gained increased attention recently due to the high data rate communication systems developed to operate in this band. The paper presents measurement results of fading characteristics, multipath parameters and background interference for these frequencies. Some statistical analysis of the measured data is presented. The paper provides information that may be useful in design and deployment of communication systems operating in the 2.4 GHz ISM band, like those compliant with IEEE 802.11 standard and Bluetooth open wireless standard

    Tadeusz A. Wysocki, Hans-Jurgen Zepernick
    84-90