Prospects and Development of Vertical Normally-off JFETs in SiC

Authors

  • Mietek Bakowski

DOI:

https://doi.org/10.26636/jtit.2009.4.958

Keywords:

JFET cascode, normally-off, SiC, vertical JFET

Abstract

This paper reviews the prospects of normally-off (N-off) JFET switch in SiC. The potential of selected vertical JFET concepts and all-JFET cascode solutions for N-off operation is analyzed using simulations. The performance of analyzed concepts is compared in terms of blocking voltage, specific on-state resistance, maximum output current density and switching performance in the temperature range from 25°C to 250°C. The main objective of the analysis is to ascertain consequences of different design and technology options for the total losses and high temperature performance of the devices.

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Published

2009-12-30

Issue

No. 4 (2009)

Section

ARTICLES FROM THIS ISSUE

License

Copyright (c) 2023 Journal of Telecommunications and Information Technology

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
M. Bakowski, “ Prospects and Development of Vertical Normally-off JFETs in SiC”, JTIT, vol. 38, no. 4, pp. 25–36, Dec. 2009, doi: 10.26636/jtit.2009.4.958.

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