The influence of yield model parameters on the probability of defect occurrence

Authors

  • Michał Rakowski
  • Witold A. Pleskacz

DOI:

https://doi.org/10.26636/jtit.2007.3.840

Keywords:

yield model parameters, spot defect, probability of defect occurrence, critical area

Abstract

This paper describes the analysis of the influence of yield loss model parameters on the calculation of the probability of arising shorts between conducting paths in IC’s. The characterization of the standard cell in AMS 0.8 μm CMOS technology is presented as well as obtained probability results and estimations of yield loss by changing values of model parameters.

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Published

2007-09-30

Issue

No. 3 (2007)

Section

ARTICLES FROM THIS ISSUE

License

Copyright (c) 2023 Journal of Telecommunications and Information Technology

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
M. Rakowski and W. A. Pleskacz, “The influence of yield model parameters on the probability of defect occurrence”, JTIT, vol. 29, no. 3, pp. 101–104, Sep. 2007, doi: 10.26636/jtit.2007.3.840.