Network-on-Multi-Chip (NoMC) with Monitoring and Debugging Support
DOI:
https://doi.org/10.26636/jtit.2011.3.1161Keywords:
debugging, FPGA, multi-chip, NoC, video codingAbstract
This paper summarizes recent research on network-on-multi-chip (NoMC) at Poznań University of Technology. The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A multicast transmission also enables real-time packet monitoring. The introduced features of NoC network allow to elaborate a model of hardware video codec that utilizes distributed processing on many FPGAs. Final performance of the designed network was assessed using a model of AVC coder and multi-FPGA platforms. In such a system, the introduced multicast transmission mode yields overall gain of bandwidth up to 30%. Moreover, synthesis results show that the basic network components designed in Verilog language are suitable and easily synthesizable for FPGA devices.
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References
[1] C. Hilton and B. Nelson, „PNoC: a flexible circuit-switched NoC for FPGA-based systems”, IEE Proc. Comput. Digit. Tech., vol. 153, no. 3, pp. 181-188, May 2006.
View in Google Scholar
[2] J. Henkel, W. Wolf, and S. Chakradhar, „On-chip networks: a scalable, communication-centric embedded system design paradigm”, in Proc. 17th Int. Conf. VLSI Design, 2004, pp. 845-851.
View in Google Scholar
[3] P. Subramanian, J. Patil, and M. K. Saxena, „FPGA prototyping of a multi-million gate system-on-chip (SoC) design for wireless USB applications”, in Proc. Int. Conf. Wirel. Commun. Mob. Comput. Connect. World Wirel., Leipzig, Germany, 2009.
View in Google Scholar
[4] Information Technology Coding of Audio-Visual Objects, Part 10: Advanced Video Coding. ISO/IEC FDIS 14496-10.
View in Google Scholar
[5] A. Lankes, T. Wild, and A. Herkersdorf, „Hierarchical NoCs for optimized access to shared memory and IO resources”, in Proc. 12th Euromicro Conf. Digit. Sys. Design DSD 2009, Patras, Greece, 2009, pp. 255-262.
View in Google Scholar
[6] R. Holsmark, S. Kumar, M. Palesi, and A. Mejia, „HiRA: a methodology for deadlock free routing in hierarchical networks on chip”, in Proc. 3rd ACM/IEEE Int. Symp. Netw.-on-Chip, La Jolla, USA, 2009, pp. 2-11.
View in Google Scholar
[7] C. Püttmann, J.-C. Niemann, M. Porrmann, and U. Rückert, „GigaNoC - a hierarchical network-on-chip for scalable chip-multiprocessors”, in Proc. 10th Euromicro Conf. Digit. Sys. Design DSD 2007, Lübeck, Germany, 2007, pp. 495-502.
View in Google Scholar
[8] X. Leng, N. Xu, F. Dong, and Z. Zhou, „Implementation and simulation of a cluster-based hierarchical NoC architecture for multi-processor SoC”, in Proc. IEEE Int. Symp. Commun. Inform. Technol. ISCIT 2005, Beijing, China, 2005, vol. 2, pp. 1203-1206.
View in Google Scholar
[9] WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores. Revision: B.3, Sept. 2002.
View in Google Scholar
[10] E. Salminen, A. Kulmala, and T. D. Hämäläinen, „Survey of network-on-chip proposals”, White Paper, OCP-IP, March 2008.
View in Google Scholar
[11] A. Łuczak, M. Kurc, and J. Siast, „Szeregowy interfejs komunikacyjny dla układów FPGA serii Virtex”, Pomiary Automatyka Kontrola, vol. 56, no. 7, 2010 (in Polish).
View in Google Scholar
[12] A. Łuczak, M. Kurc, M. Stępniewska, and and K. Wegner, „Platforma przetwarzania rozproszonego bazująca na sieci NoC”, in XII Konf. Nauk. Reprogramowalne Układy Cyfrowe, Szczecin, Poland, May 2009 (in Polish).
View in Google Scholar
[13] H. Yi, S. Park, and S. Kundu, „A design-for-debug (DfD) for NoC-Based SoC debugging via NoC”, in Proc. 17th Asian Test Symp., Sapporo, Japan, 2008, pp. 289-294.
View in Google Scholar
[14] M. Stępniewska, A. Łuczak, and J. Siast, „Network-on-multi-chip (NoMC) for multi-FPGA multimedia systems”, in Proc. 13th Euromicro Conf. Digit. Syst. Des. DSD 2010, Lille, France, 2010.
View in Google Scholar
[15] M. Stępniewska, O. Stankiewicz, A. Łuczak, and J. Siast, „Embedded debugging for NoCs”, in Proc. 17th Int. Conf. Mixed Design of Integr. Circ. Sys., Wrocław, Poland, June 2010.
View in Google Scholar
[16] A. Łuczak and J. Siast, „Network-on-chip with multicast transmission support”, to be published.
View in Google Scholar
[17] A. Łuczak, M. Stępniewska, and J. Siast, „Hierarchical addressing with hot-plug support in Network-on-Multi-Chip”, to be published.
View in Google Scholar
[18] H. Yi, S. Park, and S. Kundu, „On-chip support for NoC-based SoC debugging”, IEEE Trans. Circ. Sys., vol. 57, no. 7, pp. 1608-1617, 2010.
View in Google Scholar
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